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DS1982
CRC GENERATION
The DS1982 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can
compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within
the DS1982 to determine if the ROM data has been received error-free by the bus master. The equivalent
polynomial function of this CRC is: X 8 + X 5 + X 4 + 1.
Under certain conditions, the DS1982 also generates an 8-bit CRC value using the same polynomial
function shown above and provides this value to the bus master to validate the transfer of command,
address, and data bytes from the bus master to the DS1982. The Memory Function Flow Chart of Figure
6 indicates that the DS1982 computes an 8-bit CRC for the command, address, and data bytes received
for the Write Memory and the Write Status commands and then outputs this value to the bus master to
confirm proper transfer. Similarly the DS1982 computes an 8–bit CRC for the command and address
bytes received from the bus master for the Read Memory, Read Status, and Read Data/Generate 8-Bit
CRC commands to confirm that these bytes have been received correctly. The CRC generator on the
DS1982 is also used to provide verification of error-free data transfer as each page of data from the 1024-
bit EPROM is sent to the bus master during a Read Data/Generate 8-bit CRC command, and for the 8
bytes of information in the status memory field.
In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value
using the polynomial function given above and compare the calculated value to either the 8-bit CRC
value stored in the 64-bit ROM portion of the DS1982 (for ROM reads) or the 8-bit CRC value computed
within the DS1982. The comparison of CRC values and decision to continue with an operation are
determined entirely by the bus master. There is no circuitry on the DS1982 that prevents a command
sequence from proceeding if the CRC stored in or calculated by the DS1982 does not match the value
generated by the bus master. Proper use of the CRC as outlined in the flow chart of Figure 6 can result in
a communication channel with a very high level of integrity. For more details on generating CRC values
including example implementations in both hardware and software, see the Book of DS19xx iButton
Standards.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10
MASTER T X "RESET PULSE"
MASTER R X "RESET PULSE"
RESISTOR
MASTER
DS1982
480 ? s ? t RSTL < *
480 ? s ? t RSTH < ? (includes recovery time)
15 ? s ? t PDH < 60 ? s
60 ? s ? t PDL < 240 ? s
* In order not to mask interrupt signaling by other devices on the 1-Wire bus, t RSTL + t R should always be less than 960 ? s
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